Sr MTS Elect Design Engr

Cypress Semiconductor Technology India Pvt. Ltd
Posted

Post Expires

Type

Executive / senior industry position

 

The Chip Integration Center team is searching for a hands-on, team oriented Physical Design Methodology engineer with a proven track record. In this role, the engineer will work with the Implementation Engineers to understand the PPA (power, performance and area) targets and establish/enhance methodologies to achieve SoC PPA targets for existing and upcoming platforms. You will also drive optimizations through custom solutions or through engagement with the EDA vendors that will continuously improve the Physical Design methodologies and make the execution more efficient. Work closely with the SoC execution teams to enable quick assimilations of optimizations.. We are looking for a self-motivated and experienced engineer who can work with minimal supervision in our PD team and be able to work closely with cross functional teams.

Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis and Place & Route Experience in developing and implementing Power grid and Clock specifications, Collaborate with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools Proven Understanding of scripting languages such as Perl/Tcl Working knowledge of Extraction and STA methodology tools. Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at block and Full chip level.

  • Hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and Full Chip  designs.
  • Hands-on experience with commercial place & route tools like Cadence-lnnovus or Atoptech-Aprisa is a must.
  • Hands-on experience with commercial extraction tools like StarRC
  • Good understanding of timing, power and area trade-offs.
  • Handled Netlist to GDS II at SoC level for multiple tape outs 
  • Hands-on experience on technology nodes like 65nm, 40nm
  • Hands-on experience on physical verification (DRC/ LVS/ ERC/antenna) checks and other reliability checks (IR /EM/ Xtalk) 
  • Hands-on experience of PNR ECO flow.
  • Excellent analytical skills and the ability to think out-of-the-box to develop innovative strategies.
  • Ability to communicate, influence cross functional teams.
  • Excellent communication skills, Maturity and self-confidence, A team player with an easy-to-work-with attitude. Self-motivated, independent and resourceful problem solver.

Skills

 

  • Hands on Netlist-to-GDS implementation
  • Interpersonal skills to lead a cross-divisional and cross-functional team discussions.
  • Should be a team player
  • Capable of leading high performance teams

 

Note

Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran.

TO ALL RECRUITMENT AGENCIES: Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

Job Segment: Design Engineer, Engineering

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Posted

Post Expires

Type

Executive / senior industry position

Bengaluru%2C%20India

Bengaluru , India